1. Field of the Invention
The present invention relates to a process in which Metal Oxide Semiconductor Field Effect Transistors, (MOSFET), devices are fabricated using specific semiconductor fabrication techniques to increase the performance of the device.
2. Description of the Prior Art
Very large scale integrations, (VLSI), has allowed the electronics industry to reduce cost while continuing to increase chip performance and chip reliability. Advances in lithographic equipment, as well as lithographic processing materials and techniques have allowed the industry to produce a dynamic random access memory, (DRAM), chip with a density approaching 256 million transistors per chip. The increased performance, resulting from reducing the device dimension, can have a negative effect on device reliability. For example device performance is enhanced as the channel region, the region under the gate electrode between the source and drain, is reduced. However the chances of a "hot electron", or impact ionization phenomena is increased due to shorter channel lengths. This phenomena can result in severe degradation to the gate oxide during the lifetime of the device thus resulting in reliability failures. Therefore the semiconductor industry has had to develop structures and processes that allow for shorter channel lengths, (enhanced performance), without risking reliability in the form of hot electron degradation.
The hot electron effect is a function of channel length, gate oxide thickness, and the dopant concentration of the source and drain regions. Since increasing channel length, or gate oxide thickness, would deleteriously impact device performance, the industry resolved the performance - reliability trade-off by engineering or optimizing the source and drain regions. The higher dopant source and drains are needed to reduce resistance, however the phenomena of impact ionization increases with increasing source and drain dopant concentrations. One method developed to maintain a short channel region while reducing the risk of hot electrons, is via the use of a lightly doped drain, (LDD), invented by Ogura et al in U.S. Pat. No. 4,366,613. This process allows the channel region to be established by a lower concentration source and drain. One example of an LDD process consists of establishing the channel length via ion implantation of a lightly doped region, defined by the polysilicon gate image. After formation of an insulator sidewall on the polysilicon gate, a higher doped ion implantation is performed to serve as the contact region for the source and drain. Therefore this process, sometimes called "drain engineering", results in narrow channel lengths for performance, low resistance source and drains for contacts, with a reduced risk of hot electron reliability failures.
There are several versions of LDDs now being used for MOSFET fabrication. This invention will show a novel technique of fabricating an LDD MOSFET in which the process not only reduces reliability risks but also uses a process in which the LDD process reduces the final channel length.